PeRT3 硬件平臺 |
PER-R008-S01-X |
PER-R008-10U-X |
PeRT3 Test Suite Options |
SAS-R006-004-A |
SAT-R006-004-A |
PCI-R008-004-A |
USB-R008-001-A |
PeRT3附件 |
PER-AC12-C01-X |
PER-AC12-M01-X |
PER-AC06-Q01-X |
PER-R008-ACS-X |
PER-R008-ISI-X |
Annual Calibration of PeRT3 Systems |
PER-CA08-001-C |
Bundled Warranty and Calibration of PeRT3 Systems |
PER-CA08-W01-W |
PER-CA08-WX1-W |
新問題的新解決辦法
許多下一代高速串行標(biāo)準(zhǔn)，協(xié)議層可優(yōu)化物理層，比如為長且有噪聲的傳輸通道設(shè)置合理的發(fā)送接收均衡。這需要PeRT3這類新型儀器來執(zhí)行標(biāo)準(zhǔn)的接收測試，以及在協(xié)議層上和發(fā)送端進(jìn)行通信。因此PeRT3可用于集成的發(fā)送端和接收端測試，優(yōu)化測試時(shí)間，降低設(shè)備數(shù)量和連接復(fù)雜性。
什么是協(xié)議支持能力
帶協(xié)議支持能力的BERT系統(tǒng)，是能夠和被測設(shè)備進(jìn)行協(xié)議握手，例如均衡訓(xùn)練，并執(zhí)行電氣特性測量的儀器。
什么是PeRT3
PeRT3結(jié)合了BERT系統(tǒng)的物理層測試能力，以及和被測物進(jìn)行協(xié)議握手和訓(xùn)練的能力。
關(guān)鍵特性
· 帶協(xié)議支持能力的誤碼率測試儀
· 可用于接收機(jī)抖動和容限測試的抖動生成功能。
· 內(nèi)置3階去嵌發(fā)生器
· 支持協(xié)議的發(fā)生器和接收機(jī)狀態(tài)機(jī)
· 用戶可自定義測試腳本，用于抖動容限、均衡優(yōu)化，搜索和多參數(shù)的掃描測試。
· 用戶可自定義協(xié)議握手和訓(xùn)練的狀態(tài)機(jī)。
Generator Data Out |
| Generator Jitter Stress | ||
Bit Rate | 1 Gb/s to 8.5 Gb/s | Random Jitter Source | ||
Step Size | 100Khz | 10 Khz – 1.5Mhz RMS Jitter | 1.2 – 9 pSec RMA | |
Rise/Fall Time (20-80%) | 35 pSec typical | 1.5 Mhz- 100Mhz RMA Jitter | 1.2 – 12 pSec RMS | |
Differential Amplitude Range | 50mV to 2.2V, 5mV steps | 1.5 Mhz – 1000Mhz RMS Jitter | 1.2 – 12 pSec RMS | |
Voltage Offset | -2V to +2V | Sinusoidal Jitter Source | ||
Intrinsic Jitter | 12 pSec pp typical with internal clock | 10 Khz- 100Khz Jitter | 100 – 15000 pSec | |
De-Emphasis |
| 100Khz – 500Khz Jitter | 100 – 2000 pSec | |
# taps | 3 | 0.5 Mhz – 1000Mhz Jitter | 0 – 300 pSec | |
Range | -0.5dB to -9dB | Common Mode Source | ||
Step | 0.1dB | 100Mhz – 1000Mhz Jitter | 50 – 350 mV | |
SSC Support | 23Khz-33Khz |
| Sinusoidal waveform | |
| -5000ppm to +5000ppm | Differential Mode Source | ||
| Triangular/Sinusoidal waveforms | 100Mhz – 2500Mhz Jitter | 0 – 30 mV | |
Connector: | K-Type female |
| Sinusoidal waveform | |
Interface | Differential or single-ended, DC coupled, 50 ohm | External Jitter Injection | ||
Single error inject: | Adds single error on demand | Frequency range | 0.5 ~ 100 Mhz | |
Generator Clock Out | Modulation range | 1 ~ 200 pSec | ||
Clock Rate | At rate divided by any integer between 1-255 | Input impedance | 50 ohms | |
Duty cycle | 40-60% | Amplitude range | 60-600 mV | |
Amplitude | 0.1 Vpp-Diff to 2Vpp-Diff | Interface | DC coupled, 50 ohms | |
Output voltage window | -2V-2V | Connector | SMA female | |
Interface | Differential or single-ended, DC coupled, 50 ohm | Data In | ||
Connector | SMA female | Data Rates | 1 Gb/s to 8.5Gb/s | |
|
| Input impedance | 50ohms | |
Protocol Supported | Amplitude range | 200 – 1800 mV | ||
PCI Express | 2.5, 5 and 8 Gb/s | Clock In | ||
SAS | 1.5, 3 and 6 Gb/s | Frequency range | 1 Ghz to 8.5 Ghz | |
SATA | 1.5, 3 and 6 Gb/s | Termination | 50 ohms | |
USB3.0 | 5Gb/s | Amplitude range | 600 – 1200 mV | |
| Tigger Out | |||
Amplitude range | 600 – 800 mV | |||
ISI | External | |||
