Introspect DP/eDP碼型產生器（Pattern Generator）：
DP/eDP Generator信號發(fā)生器支持目前The latest in the industry的DP2.0/eDP V1.5 的速率，支持多通道測試，是業(yè)界only能夠同時支持從物理層至協(xié)議層功能性測試的解決方案，支持PSR/PSR2, ALPM, 抖動注入、Skew、電壓幅值、時序等相關功能的測試驗
Introspect DP/eDP碼型產生器（Pattern Generator）：
DP/EDP碼型發(fā)生器，DP/EDP信號發(fā)生器，EDP信號發(fā)生器，DP信號發(fā)生器，EDP碼型發(fā)生器，DP碼型發(fā)生器，DP/EDP接收機測試，DP接收機測試，EDP接收機測試，EDP Pattern Generator, DP Pattern Generator,DP/EDP Pattern Generator，DP/EDP信號質量測試
DP/eDP Generator信號發(fā)生器支持目前The latest in the industry的DP2.0/eDP V1.5 的速率，支持多通道測試，是業(yè)界only能夠同時支持從物理層至協(xié)議層功能性測試的解決方案，支持PSR/PSR2, ALPM, 抖動注入、Skew、電壓幅值、時序等相關功能的測試驗證。
DP/EDP碼型發(fā)生器（Pattern Generator）是目前各大主流的SoC，DDIC等廠商用于DP/EDP接口測試驗證的方案。
Overview:
The SV5C-eDP Embedded DisplayPort Generator is an ultra-portable, high-performance instrument capable of generating traffic for Embedded DisplayPort and DisplayPort applications at data rates of up to 8.1 Gbps. The SV5C-eDP Generator provides analog parameter controls that enable DisplayPort receiver stress-testing and allow for deep insights into voltage and timing sensitivities of DisplayPort sink devices. The instrument operates with the award-winning Introspect ESP Software environment which includes full pattern synthesis tools for generating test patterns and video frames for system-level test.
Figure 1 below illustrates a typical application of the SV5C-eDP Generator in an Embedded DisplayPort system.
Key Features:
• Protocol: supports Embedded DisplayPort (eDP) up to v1.4 and Display Port (DP) up to v1.4
• Supported Data Rates: up to 8.1 Gbps with a fully continuous range of data rates
• Lane Count: configurable from 1 to 4 lanes per port plus Auxiliary Channel
• Analog Controls: voltage amplitude and common mode voltage, each per lane
• Signal Impairments: jitter injection, sinusoidal voltage noise injection, per-wire timing skew
• Pattern Generation: full video frame generation with 2 GBytes of pattern memory
